The present invention relates to the manufacture of semiconductor devices, and more particularly to a method for forming vias in semiconductor devices.
A continuing trend in semiconductor manufacturing is to make more powerful and complex integrated circuit devices in a smaller area. Manufacturers achieve this objective by making individual feature sizes smaller and by locating these features closer together. Millions of active and passive devices, such as transistors, capacitors, and resistors are formed on a semiconductor substrate, such as silicon. These devices are isolated from each other on the substrate and later are interconnected to form functional circuits. The quality of these interconnecting structures drastically affects the performance, and reliability of the completed circuits.
Often the interconnections are fabricated as a multilayer structure having alternating layers of patterned metal and dielectric materials. The dielectric layers, frequently a form of silicon oxide, serve to separate the conductors, both vertically and horizontally, and very small, vertical metal filled vias provide a means of interconnection between the metal levels. Performance of the interconnections and dielectric must be precise and predictable in order to provide a stable device.
In multilevel structures, the metal conductors may include a base layer, a bulk conductor layer, and a capping layer, and the sum of these layers is referred to as a metal stack. The metal stack is formed on a dielectric layer, typically by sputtering, and then through the use of photolithographic techniques is etched to define the interconnecting structure. Aluminum and aluminum alloys are often used as the bulk conductors in metal stacks.
As a result of the small size and complexity of vias, particularly for 0.35 micron and smaller technology, fabrication and integrity often present a significant challenge to the manufacture, yield, and reliability of modern ultra large scale integrated circuits.
A simplistic via structure, as shown in FIG. 1, typically includes a horizontal metal interconnection layer 101, most frequently comprised of aluminum, copper, or an aluminum alloy, one or more dielectric layers 102, usually some form of silicon dioxide, and a conductive metal plug 103 in the via, such as tungsten (W). In complex devices, the metal level may be comprised of multiple layers of material, including currently popular titanium (Ti) and titanium nitride (TiN) which sandwich the conductive interconnection metal. The layers 104, 105 serve multiple purposes which may include adhesion promotion, antireflection, and an aid in defining grain structures. Also, it has been found that for proper orientation and formation of the TiN layer, it is necessary to first provide a clean surface of a titanium metal layer 105 which acts as a seed layer.
However, due to the interaction of aluminum and/or copper with other materials, a barrier layer 107 is usually provided between the metal interconnection layer and via plug. A typical via-barrier layer 107, such as CVD deposited TiN which conforms to the inner surfaces of the via prior to forming the tungsten plug.
Obviously, misalignment of the metal stack can lead to exposure of the plug metal, and in turn to corrosion during subsequent processing. Poor coverage of the metal by the barrier metal can lead to voids in the interconnection resulting from the tungsten source gas interacting with aluminum. A number of other via failure mechanisms have been disclosed, along with proposed corrective procedures.
A more subtle yield loss related to via integrity has plagued the industry, wherein via resistance may be marginally high, but more importantly an instability in the operating frequency has lead to both yield and operating failures of the device. Such subtle failures are difficult to detect and to control, but stress induced extrusion of aluminum into the via has been identified in xe2x80x9cReflow of AlCu into Vias during CVD TiN Barrier Depositionxe2x80x9d, A, Oliva, et.al., ISRM2000, and Besser, et al in U.S. Pat. No. 5,789,315 (1998) as one contributor to such device reliability degradation.
A schematic drawing of a metal extrusion failure is illustrated in FIG. 2. The metal conductor 201 having a relatively high coefficient of thermal expansion is constrained and put into a state of compression by the dielectric layers 202 of the via which have a much lower expansion coefficient. During thermal excursions, some of the metal stress may be relieved by an extrusion 206 through the barrier layers 204 into the base of the via. While it is agreed that the failure is related to a thermally induced compressive stress in the metal line which causes the metal to extrude into the via to relieve stress, a clear solution for elimination of the defect has not been previously identified.
It is an object of the current invention to provide a method for elimination of metal extrusions through the barrier layers of etched via holes in multilevel integrated circuit devices.
It is an object of the invention to identify the root cause of stress induced extrusions into vias, and to provide a method for eliminating the source of the failure.
It is an object of the invention to provide an improved manufacturing process for via barrier formation.
It is an objective of the invention to provide a manufacturing process which does not slow throughput.
It is an object of the invention to provide a manufacturing process for elimination of metal extrusions through the barrier layer, and into the via which is not related, and dependent upon a second variable or process.
It is an object of the invention to provide a method for manufacture of semiconductor devices which improves yield and reliability.
It is an object of the invention to provide a method for elimination of stress induced metal extrusions into vias which is applicable to different metal stacks.
It is further an objective of the invention to provide a method of eliminating stress induced metal extrusions into vias which is not dependent on barrier thickness.
It is an object of the invention to provide an interconnection metallization, including titanium aluminide, wherein good integrity of the via barrier against metal extrusions is exhibited.
The above and other objectives of the invention will be met by disclosing a process whereby metal extrusion through the via barrier layer into the base of an etched via holes is eliminated. Temperature of the in process wafer, and that of the via barrier deposition is controlled at less than 400xc2x0 C., and preferably to about 380xc2x0 C., thereby decreasing compressive stresses on the metal at the process step where the failure is manifested.
By eliminating the cause of metal extrusions, i.e., excessive thermally induced stresses on the metal confined biaxially by the dielectric via walls, the resulting defect free vias are independent of the barrier thickness, the method is applicable to different metal stacks, and in turn yield and reliability of the device is significantly enhanced.